Entry level DV Engineer.
Riseedge is looking for a OPT/STEM entry level DV engineer.The position is focused in Functional Design Verification using System Verilog and UVM. The self motivated engineer will contribute to DV tasks working closely with DV team.
Responsibilities:
- Develop directed/constrained-random test, sequences using UVM
- Assist in analyzing regression failures, debug
- Ability to debug python scripts.
Qualifications:
- MSEE OPT/STEM
- prior 2yrs of work experience is desirable but not required.
- prior SystemVerilog or similar HVL’s is a plus.
DV Engineer.
RiseEdge provides Design services. In the dynamic fast-paced environment you will get to learn fast and contribute to the success of the company.
Job Description We are looking for Part-Time/CW Design Verification Engineer to provide DV services.
Responsibilities:
• Testbench development using UVM for logical blocks and verification infrastructure.
• perform testplan creation, writing sequences, assertions, and tests.
• VIP integration and develop scoreboards.
• Regression & debugging test failures.
• Coverage collection and closure, verification convergence.
• Integration of Lower-level Benches to SoC.
Required Skills:
• Experience with SV and UVM methodology.
• Hands on experience on UVM bench development, cycled through couple of verification convergence tasks.
• Self Driven and take initiative, Able to work closely with DV team.
• python is a plus.
Qualifications:
- MSEE with upto 2 years in DV experience.
- Strong background in SV and HDL’s.