Our Services

RiseEdge has specialized experience in silicon development,Offers SoW or Individual ASIC services delivering on meeting customer criteria.

Read More

Functional Verification

End-to-End Verification from Architecting Environments, Testplan creation to verification Sign-OFF.

DFX

End-to-End DFT Solution. Analyze Testability of Design, Write DFT Spec., Implementation and Execution of DFT flow, ATPG to ATE production patterns.

IP Sub-Systems

Integrate HighSpeed DesignWare IP’s to Subsystems. Execute Front-End Implementation Flow RTL to Netlist HandOff.

Front-End Flow

Low-Power Synthesis, Constraints, STA Timing Closure.

Read More

Our Solutions

RiseEdge delivers cutting edge solutions in end2end ASIC from Specification to sign-off for various chip technologies and applications.

  • Low Power Verification

  • Mixed Signal AMS Verification

  • SoC Integration

  • LPDDR4, PCIe Gen5 Interconnect

  • DFT Architecture

  • Implementation Flow Automation

view All Solutions

Client Testimonials

Raghu worked as a DV engineer for our team across two projects over many years. During his time, he mainly focused on UVM Block Level DV of our external interfaces, but he also helped us in many other areas such as: top level RTL & GLS verification, code coverage analysis, and ramping up other new engineers. He was easy to work with and the blocks he worked on came back from the fab with no critical bugs. I would love to work with Raghu again in the future.

David Du Senior Director of Engineering, IC Design, NXP Semiconductor

I  thank  Raghu for the hard work to develop and verify the PCIe gen5.0 CXL bring-up & constraints handoff.  There were many challenges and Raghu diligently work through each of them on a demanding schedule.  Raghu helped greatly to push Synopsys IP vendor while also adapting  meet the particular needs of our environment.  Your efforts on this are greatly appreciated!

James Bandy Sr. Design Manager, Maxlinear Inc

Raghu was responsible for DFT implementation for a complex interface IP subsystem while working in the team that I managed. He worked with the customer to understand the requirements and architected a solution using state-of-the-art compression techniques. Raghu developed the DFT insertion scripts from scratch and achieved target ATPG coverage. Raghu also helped develop scan mode timing constraints and set up gate-level pattern simulations. Raghu completed all the work on time and ensured that the customer could seamlessly integrate the subsystem in their SoC.

Shoumik Maiti Design Manager, Synopsys

I’m happy to recommend Raghu for Design Verification. I’ve worked directly with Raghu in the past few years, and can attest to his abilities to do a complete and thorough job. He complete rewrote the test environments for several IPs, achieved complete coverage, resulting in bug free silicon.

Brian Flanagan Master Engineer, NXP

I reached to Brunda for a contracting position. She did exactly what we need, and an asset to the team. I recommend for any verification role.

Steve Design Manager, Dialog Semi-Conductor

I had the pleasure of working with Raghu while he was at Aeva. Raghu was responsible for verifying the High-Speed and Low-Speed Analog Front End blocks of the SoC. He worked with the 3rd part IP vendor to fully understand the block and created comprehensive test plans for both the blocks and UVM test benches to verify the blocks. He was able to achieve close to 100% coverage on the blocks. Raghu completed his tasks on time and was very detailed when doing the knowledge transfer. I would recommend Raghu for any DV role and would not hesitate to work with him again.

Sowmya Ramakrishna Design Manager, Aeva

About Us

RiseEdge has enriching experience with proven track record in Design Verification, DFX and IP integration enabling faster development cycles and focus on achieving customer goals.

Read More