Verification
- Verification Planning, Creating Test Plans working with cross functional teams.
- Re-use of Block, Subsystem level environments to Chip Level.
- Integrating Vendor VIP’s and IP level benches.
- Porting tests from lower-level to chip Level.
- Matlab and C Models for bit-matching.
- Core level Co-Simulation environments.
- Coverage Model, Metrics definition and convergence.
- Mixed Signal Interface Specific checks.
- Chip Low-Power Mode Sequences.
- Developing constrained random tests and use cases.
- Automation of Verificaiton tracking and Sign-Off.
DFX
- Extensive experience in Architecting DFT of Complex SoC’s.
- Derive detailed DFT Specification from Chip Topology
- Implement/Automate TCL scripts for Scan Compression & OCC.
- Integrate Core-Level Scan to SoC.
- Integrate IEEE1500, MBIST engines on RTL or GATES.
- ATPG flow for all fault models.
- Pattern Simulation and automate ATE program.
Frond-End Flow Automation
- Constraints development, porting/merging to Top.
- DC-Topo/Low-Power Synthesis.
- Spyglass, CDC, formal checks.
- Handoff Netlist Delivery and Checklists.
- Timing Closure, STA & PD support
IP Subsystems.
- Vendor IP LPDDR4/PCIE Gen4 PHY and Controller Integration.
- Porting Vendor IP verification env. to higher level.
- Integrate IP level Coverge Metrics to Chip.
- RTL integration of vendor Memories.
- Setup and Execute Implementation Flow.
- Execute BIST & Scan Solutions.
- Netlist and Constraints HandOff.
