Raghu Garikapaty
Raghu Garikapaty has spent two decades in chip design and product development. He is primarily focused on Design Verification Sign-Off. Raghu lead and driven end-to-end verification of multiple SoC’s from verification planning, criteria, coverage closure, task alignment and verification convergence.
Raghu started his career with chip implementation and worked extensively on chip integration, synthesis, DFT, STA sign-off and Flow Automation. He was a DFT Architect, lead end-to-end DFT execution from specification definition to ATE successfully on production chips. He has Successful track-record in tape-outs of many product road-map chips.
Previously held technical lead positions at STMicro, Qualcomm and Synopsys. He holds a MS degree from NIT Warangal, India.
Leadership:
Tech. Lead and Managed teams of engineers driving DV Tasks delivering high productive team results. Solution driven on achieving mile-stones, Alignment with multi-site and cross functional teams. Key-Focus on Continuous process and productivity improvement. Progress tracking of DV, DFT Convergence and reporting to C-level. Raghu has proven track record, Hands-on DV and DFT execution aspects of product development.