RISC-V Core Explorations
Ongoing feasibility studies for open-source RISC-V cores with Verilator and VCS-based simulation flows.
CVA6 / Ariane
Evaluating the CVA6 core using Verilator for RTL-level feasibility and integration checks. Focus areas include pipeline validation, memory subsystem interface, and cache coherence exploration.
Status: Ongoing — Verilator & VCS validation in progress.