Register Abstraction Layer (RAL) Verification
UVM RAL model design and validation for register read/write, reset behavior, and functional coverage.
Overview
RAL model and adapter with structured sequences for read, write, bit-bash, and reset operations. Includes error injection and masking checks to ensure coverage of corner cases in register access.
Status: Completed — verified and coverage-closed.
Flow
Complete model build flow with predictor integration, adapter mapping, and mirror validation. Functional coverage ensures all register access types and reset values meet specification.
Status: Verified using UVM RAL Framework.
Artifacts
Includes waveform snapshots, coverage summaries, and simulation logs confirming reset and access functionality. The repository also contains documentation for RAL model generation and UVM environment setup.
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